Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate

ABSTRACT

Electronic module ( 100 ), which comprises a first substrate ( 102 ), a first dielectric layer ( 104 ) on the first substrate ( 102 ), at least one electronic chip ( 106 ), which is mounted with a first main surface ( 108 ) directly or indirectly on partial region of the first dielectric layer ( 104 ), a second substrate ( 110 ) over a second main surface ( 114 ) of the at least one electronic chip ( 106 ), and an electrical contacting ( 116 ) for the electric contact of the at least one electronic chip ( 106 ) through the first dielectric layer ( 104 ), wherein the first adhesion layer ( 104 ) on the first substrate ( 102 ) extends over an area, which exceeds the first main surface ( 108 ).

BACKGROUND

1. Field

Various embodiments in general relate to an electronic module and methodfor producing of at least one electronic module.

2. Description of the State of the Art

Electronic modules can comprise one or more electronic chips which arefor example encapsulated in an encapsulation structure and can beconnected to an electronic periphery through electrically conductivecontacts.

It is also possible to produce an electronic module, while electronicchips are mounted between two metallic substrates and spaces are filledwith prepreg material. In conventional processes of the type described,high temperatures can occur, which may negatively affect the electronicchips. Even a tilt-free mounting of electronic chips between twometallic substrates is a technological challenge.

SUMMARY

There might be a need for an electronic module which can be manufacturedeasily and be robust against errors.

According to an exemplary embodiment, an electronic module is provided,which provides a (in particular, electrically conductive) firstsubstrate, a first dielectric layer on the first substrate (inparticular, electrically insulating), at least one electronic chip,which is mounted on a section of the first dielectric layer, with afirst main surface directly (i.e. with direct contact between theelectronic chip and the first dielectric layer and thus without acomponent arranged between the electronic chip and the first dielectriclayer) or indirectly (i.e. without direct contact between the electronicchip and the first dielectric layer and thus with a component betweenthe electronic chip and the first dielectric layer like, for example, anadditional dielectric structure), a second (in particular, electricallyconductive) substrate over a second main surface of the at least oneelectronic chip, and an electrical contact for making electrical contactwith the at least one electronic chip through the first dielectriclayer. The first dielectric layer can extend on the first substrate overan area, which exceeds the first main surface.

According to another exemplary embodiment example, a method forproducing at least one electronic module is provided, wherein in themethod a first adhesion layer is applied at least to an entire componentmounting area of a first substrate, a first main surface of at least oneelectronic chip is mounted directly or indirectly on a section of thefirst adhesion layer, a second substrate is applied over a second mainsurface of the at least one electronic chip, and the at least oneelectronic chip is electrically contacted through the first adhesionlayer.

According to yet another exemplary embodiment example, a method forproducing at least one electronic module is provided, wherein in themethod a first adhesion layer is applied at least to an entire componentmounting area of a first substrate, a first main surface of a pluralityof electronic chips is mounted directly or indirectly on a respectivepartial region of the first adhesion layer, a second adhesion layer isapplied to a second substrate, and a second main surface of theplurality of electronic chips is mounted directly or indirectly on arespective partial region of the second adhesion layer.

An exemplary embodiment example has the advantage that one or moreadhesion layers formed during the manufacturing method (which aftercompletion of the manufacturing method, i.e. the completed electronicmodule, in the case of an electrically insulating material of theadhesion layer is called dielectric layer) will be used for single-sidedor double-sided mounting of one or more electronic chips formanufacturing of an electronic module. This enables the mounting ofelectronic chips on the substrates by the adhesion layer(s) at lowtemperatures, resulting in a saving of electronic chips and as a resultleading to a quality improvement of the manufactured electronic modules.By providing a substantially complete or full-surface adhesion layer onat least one main surface of the electronic chip, the adhesion materialcan be provided in a very good homogeneity, especially with a veryuniform thickness, so that an unwanted tilting of an electronic chipduring the assembly on or over a such adhesion layer can be reliablyavoided. Tilting and unwanted hollow spaces inside of the electronicmodule can be avoided through the assembly technique described, becauseaccording to exemplary embodiments neither a precise dosing of adhesivematerial nor a precise positioning of adhesive material is critical.With the described assembly architecture, the number of differentmaterials and material surfaces can be kept so small, that problems withdifferent thermal expansion coefficients of different components of theelectronic module and an unwanted thermal mismatch can be avoided.According to exemplary embodiment examples, the manufacturing method canbe made easily, and a list of required components and materials can bekept small.

One or preferably two-sided large-area applying of a relevant adhesionlayer on the respective substrate, for preferably sandwiching of theelectronic chip(s) between two substrate adhesion layer stacks, hastechnical advantages. From one side, the applying of planar andessentially continuous adhesion layers leads to an improved protectionof electronic chips against tilting during assembly and againstundesired moving caused by force of adhesion of the electronic chip(s)from a desired position of adhesion. Large planar layers of adhesionmaterial provide for a more tolerant positioning in this respect andhave less tilt inclination for chips during the chip assembly. Alsoproviding a large adhesion layer significantly extending over theelectronic chips allows a simple and slight position-critical placementof the electronic chips and therefore results in total in less alignmenteffort. If the adhesion layer(s) is or are designed essentiallyfull-surface in the component assembly area of the substrate(s), it orthey can perceive its or their adhesive function for various modulecomponents across a larger area, resulting in a reduced risk of unwantedhollow spaces inside of the electronic module. Through optionalproviding of dielectric structures (also denoted as fill structures orlaminate structures, for example so called prepregs) for filling outhollow spaces in the electronic module, a large adhesion layer canmanage or support not only the mounting of the electronic chip to therespective substrate, but even the mounting of the dielectric structureon substrate and/or electronic chip. Furthermore, even the number ofused dielectric structures can be reduced or kept small.

DESCRIPTION OF OTHER EMBODIMENT EXAMPLES

In the context of the present invention, the term “adhesion layer” canindicate in particular an extended and continuous layer with an eventhickness of an adhesive material. The adhesive material can be sodesigned, that if an electronic chip (or other module component) ismerely placed on the adhesive material, a mounting connection betweenthe electronic chip (or the other module component) and the adhesionlayer will be formed. In particular polymer, for example epoxy or filledepoxy, can be used as adhesion material of the adhesion layer.

In the context of the present invention, the term “dielectric layer” candescribe in particular a layer composed of electrically insulatingmaterial that has been manufactured from the adhesion layer and formspart of the completed electronic module. Through a hardening of at leasta part of the adhesion layer during manufacturing process, it can loseits adhesive nature entirely or partially and will therefore beindicated in the context of this application as a component of thecompleted electronic module, also as the dielectric layer.

In the context of the present invention, the term “component mountingarea” can in particular indicate a surface area of the respectivesubstrate, on which the functional components (in particular thechip(s), if applicable, a dielectric structure, etc.) of themanufactured electrical module(s) shall be mounted. In other words, thecomponent assembly area forms at the end of the manufacturing processpreferably a part of completed electronic module. A ring-shaped outermargin area of the substrate cannot belong to the preferablyfull-surface component mounting area, which shall be covered with theadhesive material, which can remain free of adhesion material (but mustnot) and from which no electronic modules must be obtained. Alsooptional alignment markers (“alignment markers”), which during themanufacturing process are used as orientation and/or positioning helpfor equipment to be able to perform certain procedures (for example,place of a chip assembly, definition of areas of etching, etc.)especially with exact position, cannot belong to the preferablyfull-surface component mounting area, which shall be covered with theadhesive material.

According to an exemplary embodiment, an ultra-thin electronic modulecan be manufactured, for example, from at least two electronic chips,wherein one of the chips can be oriented in one direction and the othercan be oriented in the opposite direction. Such an electronic module isable to withstand high currents and currents which are flowing in thevertical direction (for example 10 amperes and more), wherein a lowresistance and a strong suppression can be obtained from parasiticeffects. With the mounting technology according to exemplary embodimentexamples, the handling of very small and very thin electronic chips inconnection with the placing and mounting of electronic chips to therespective substrate is possible easily and robust against errors,because the requirements to the accuracy of applying of adhesionmaterial are low in the terms of quantity and position. Through theapplication of a full layer of adhesive material (for example, resin) onthe respective substrate, the requirement of applying of precisequantities of adhesion material at precise positions can be elegantlyavoided. According to exemplary embodiment examples, the adhesionmaterial can be applied using silk screen. Especially when the use oftwo pressure stages of successive applying of two parallel andvertically arranged parts of layers of adhesive material, an unwantedtilting of electronic chips can be effectively suppressed, because thelower part of layer can be used for the reliable electrical insulationand the upper part of layer can be used for firmly pressing of theelectronic chips to be mounted. According to an exemplary embodimentexample, thus an embedded module can be created, at which at least oneelectronic chip will be linked to a particular pressed adhesion layer onboth sides.

Afterwards, more exemplary embodiment examples of the module and themethods will be described.

According to an exemplary embodiment example, it is possible to providean adhesion layer or dielectric layer only on one side or main surfaceof electronic chips. A version with the adhesion layer or dielectriclayer on one side can be meaningful for example, if the electronic chipsshow only one direction. Then a dielectric structure can be laminated onthe other side, for example prepreg.

According to an exemplary embodiment example, the electronic module hasa second dielectric layer on the second substrate, wherein at least oneelectronic chip is mounted with its second main surface directly orindirectly on a section area of the second dielectric layer. In theelectronic module, arranged dielectric layers can be provided thusbeneficial on both sides of the electronic chip(s), for example, ifseveral electronic chips show different or opposite directions.

The first adhesion layer or dielectric layer can be designed on thefirst substrate as a continuous adhesion layer or dielectric layer. Thesecond adhesion layer or dielectric layer can be designed on the secondsubstrate in appropriate way as a continuous adhesion layer ordielectric layer. In the context of the present intention, the term“continuous” can indicate in particular that the respective adhesionlayer or dielectric layer can be designed without isolated islands.

The first adhesion layer or dielectric layer of the electronic modulecan be interrupted, for example, only through the electrical contact(i.e. otherwise completely), otherwise can cover the entire firstsubstrate of the electronic module. The second adhesion layer ordielectric layer of the electronic module can be placed in appropriateway, interrupted only through the electrical contact (i.e. otherwisecompletely), otherwise can cover the entire second substrate of theelectronic module.

The first adhesion layer or dielectric layer can have a uniform orconstant thickness on the first substrate. The second adhesion layer ordielectric layer can have a uniform or constant thickness on the secondsubstrate in appropriate way.

The first adhesion layer or dielectric layer can extend across an areaover the first substrate, which has at least double size of the firstmain surface. The first adhesion layer or dielectric layer can contacteven a dielectric structure section by section on the first substrate(for example a prepreg). Accordingly, the second adhesion layer ordielectric layer can be extended across an area on the second substrate,which has at least double size of the second main surface. The secondadhesion layer or dielectric layer can contact even a dielectricstructure section by section on the second substrate (for example aprepreg).

According to an embodiment example, at least one of the first substrateand of the second substrate is a structured, especially metallic foil.The foil can have such low thickness, that it is flexible and thereforecan be adapted to the electronic chips to be contacted. With flat foils,a plurality of electronic chips can be used, in order to simultaneous orbatch-type manufacturing of multiple electronic modules to be connectedor mounted, so an efficient manufacturing process is allowed. In thecomplete manufactured electronic module, the respective foil as a firstor second substrate can have, for example, a thickness of 3 μm to 20 μm.During the manufacturing process of electronic chips, a thickermultilayer foil and therefore having a stabilizing effect in light ofthe handling of the thin electronic chips can be used as a firstsubstrate and a second substrate, which has a temporary carrier and aremovable functional layer thereof. The temporary carrier can have, forexample, a thickness in a range between 35 μm and 200 μm, whereas thefunctional layer, for example, can have a thickness between 5 μm and 20μm.

According to an embodiment example, at least one of the first substrateand of the second substrate is manufactured from an electricallyconductive material. If the foils are manufactured from electricallyconductive material, they can contact the electronic chips through anelectronic periphery. For example, the substrates can be produced fromaluminum or copper foils. Such substrates have also a high thermalconductivity, so the substrates can contribute to the heat removal ofthe electronic chips during the operation of the electronic module.

According to an embodiment example, the first adhesion layer ordielectric layer is made from a full-surface layer with at least oneclearance hole, filled with an electrically conductive material aselectrical contact for the electrical connection of the first mainsurface of at least one electronic chip. The clearance holes can bedesigned after the mounting of the electronic chips between the twosubstrates with a respective adhesion layer or dielectric layer, forexample by means of etching, and subsequently be designed further bymeans of cutting off of electrically conductive material to anelectrical contact to form a targeted electrical coupling of pads of theelectronic chips with the electronic periphery. To couple specificallyindividual areas of electronic chips electrically with the environmentor to decouple electrically from the environment, a respective adhesionlayer or a dielectric layer can be made advantageously of anelectrically insulating material.

According to an embodiment example, the at least one electronic chip ismounted on the first adhesion layer or dielectric layer and on thesecond adhesion layer or dielectric layer is this way that the at leastone clearance hole is adjacent to the respective of the main surfaces ofthe at least one electronic chip.

According to an embodiment example, the electronic module has aplurality of electronic chips, wherein every one of which is mountedwith its first main surface on the first adhesion layer or dielectriclayer and with its second main surface on the second adhesion layer ordielectric layer in this way, that a part of at least one of the firstadhesion layer or dielectric layer and the second adhesion layer ordielectric layer remains uncovered of the plurality of electronic chips.In other words, the area of a respective adhesion layer or dielectriclayer can be considerably larger than the sum of the respective first orsecond main surfaces of the electronic chips to be mounted thereon.Thus, due to the essentially full-surface providing of the respectiveadhesion layer or dielectric layer, a delimited mounting area isassigned not to each of the electronic chips, but rather, it is provideda continuous connected adhesion layer or dielectric layer, covering evenseveral electronic chips, what allows a manufacturability with higherhomogeneity.

According to an embodiment example, at least one of the first adhesionlayer or dielectric layer and of the second adhesion layer or dielectriclayer is designed of a polymer or a resin. Each of the adhesion layersof the dielectric layers can thus be executed as an adhesion layer, onwhich the electronic chips can be mounted without strong temperatureinfluence. It is possible that such adhesion layers will be hardenedafter mounting the chips. It is also possible that such adhesion layersbefore mounting of an electronic chip will be pre-treated to improve themounting properties, in particular at least partially pre-dried.

According to an embodiment example, the electronic module has adielectric structure (electrically insulating) in at least a hollowspace, which can be limited, for example, vertically between the firstdielectric layer and the second dielectric layer and laterally throughat least one electronic chip. Through mounting such a dielectricstructure in hollow spaces between the substrates and the mountedelectronic chip(s), unwanted empty spaces can be filled and at the sametime used advantageously for mounting of the dielectric structure on twosubstrates, from which adhesion layers of dielectric layers areextending over the chips.

In accordance with an embodiment example, the dielectric structure isdesigned as a prepreg structure. Prepreg (pre-impregnated fibers) canindicate in particular a semi-finished product made of endless fibersand an unhardened thermosetting plastic matrix, especially epoxy-coatedglass fibers. Prepreg can be obtained as sheet or wrapped on rolls. Suchprepreg structure offers the advantage that it can be manufactured in astructured way (in particular as a perforated foil with cut-outs, forexample, blind or clearance holes on the positions of the laterelectronic chips) and can be mounted between the two opposite adhesionlayers or dielectric layers. Prepreg material can be adhesive and fluidunder pressure and/or temperature influence and thus act as both theconnection structure and the dielectric structure. This allows theelectronic chips in the electronic module to be mechanically stabilizedand to fill the hollow spaces.

According to an embodiment example, at least one of the first adhesionlayer or dielectric layer and the second adhesion layer or dielectriclayer designed of a first part layer on the respective substrate and ofa separate second part layer on the first part layer. The first part oflayer ensures that a reliable electrical insulation between therespective substrate and the electronic chip is guaranteed. To enhancethe reliability in this respect, the first part of layer before applyingthe second part of layer can optionally pre-dried or otherwise treatedto increase its strength to maintain the electrical insulation duringthe chip assembly process. After placing the second part of layer, theelectronic chip can be pressed with relatively larger mounting force andthus be impressed on the second part of layer, without the risk of lossof electrical insulation, because of providing of the first part oflayer.

According to an embodiment example, the first part of layer ismanufactured on a material, which is different from a material of thesecond part of layer. Through a different choice of the materialcomposition of the two parts of layer, each of them can be optimized onits function, i.e. electrical insulation of the substrate or mounting ofelectronic chip.

According to an embodiment example, the first part of layer will bedried or partially solidified, before the second part of layer will beapplied. This increases the mechanical robustness of the first part oflayer and builds thus a reliable barrier to maintain the electricalinsulation through the first part of layer, if after that the electronicchip will be mounted on the second part of layer.

According to an embodiment example, the electronic module has twoelectronic chips, wherein one of them has its active side on his firstmain surface and the other has its active side on his second mainsurface. This allows even complex circuits to be built with lowmanufacturing effort and especially low wiring effort.

According to an embodiment example, the electronic module can have atleast one clearance hole filled with conductive material (particularlyone via), which extends vertically to the first substrate and a secondsubstrate to build an electrical coupling of the first substrate withthe second substrate. In volume ranges of the electronic module notoccupied through electronic chips, also an electrical coupling can berealized between the two substrates in vertical direction. Through suchclearance holes filled with conductive material, even pads on differentmain surfaces of electronic chips can be connected togetherelectrically.

According to an embodiment example, at least one of the first substrateand a second substrate can be structured during the manufacturingprocess, in particular by means of etching, to make thus electricallyconductive paths. The substrates are used during the manufacturingprocess as stability structures to the intermediate ordering of theelectronic chips and can be structured after completion of chip mountingto achieve desired electrical couplings and de-couplings betweenindividual components of the electronic chip.

According to an embodiment example, at least one of the first adhesionlayer or dielectric layer and the second adhesion layer or dielectriclayer be can be hardened or will be hardened. After the electronic chipis mounted on a corresponding adhesion layer, the material of theadhesion layer ca be heartened through respective handling (for example,thermal treatment, pressure treatment, etc.) to keep a mechanical solidand robust electronic module.

According to an embodiment example, the electronic module has aplurality of electronic chips, which are electrically coupled with eachother by means of the electrical contacts on at least one of the firstmain surface and on the second main surface. For a specific targetedcoupling of pads of electronic chips on laterally adjacent positions atthe same level, the built electrical contact structures can be usedacting together with corresponding sections of the respective substrate.It is also possible to manage a contacting of the specific pads ofelectronic chips through vias, which can be fitted, for example, throughthe dielectric structure.

According to an embodiment example, at least one of the first adhesionlayer and a second adhesion layer on the respective substrate will beapplied by means of pressing, in particular by means of silk-screen. Animprint of a respective adhesion layer on a particular substrate hasproven as easy way to apply an adhesion layer of homogeneous thicknesson the substrate, wherein a later incorrect mounting of electronic chipson this adhesion layer will be avoided through tilting or of that kind.

According to an embodiment example, at least one clearance hole will bemade in at least one of the first adhesion layer or dielectric layer andof the second adhesion layer or dielectric layer for the electricconnection of the respective main surface of the respective electronicchip. According to an embodiment example, during the forming of at leastone clearance hole in the respective adhesion layer or dielectric layer,even at least a corresponding clearance hole in the correspondingsubstrate will be formed. This allows access to connection pads ofelectronic chips. Beneficially, for example, a clearance hole in acommon lithography and etching method both through a specific adhesionlayer or dielectric layer and through an adjoining substrate can bemade.

According to an embodiment example, the at least one clearance hole forelectrical contacting of the respective main surface of the respectiveelectronic chip will be filled at least partially with conductivematerial. This can be done for example with a separation process.According to an embodiment example, the filling of the at least oneclearance hole with electrically conductive material will be performedby means of one of the group, which consists of current-less coating,electrochemical coating and direct metallization.

According to an embodiment example, the method has a separating of aplurality of electronic chips between the first substrate and the firstadhesion layer or dielectric layer on the one hand and the secondsubstrate and the second adhesion layer or dielectric layer on the otherhand, to a plurality of electronic modules or packages, of which any onesection of the first substrate, a section of the first adhesion layer ordielectric layer, a section of the second substrate, a section of thesecond adhesion layer or dielectric layer and at least one electronicchip. Thus, the double-sided mounting of a plurality of electronic chipscan be done in batches for a plurality of electronic modules, as well asthe filling of hollow spaces and forming of a contacting structure. Forthis, the availability of large scale foils as substrates and the use oflarge adhesion layers and dielectric layers are in particularbeneficial. After the joint, parallel processing (on chip mounting,providing a dielectric structure in form of one or more hole foils withcut-outs on positions of the respective chips, as well as and mountingthe components next to each other), a separation of the resultingarrangement in the individual or separate electronic modules can beperformed, for example, by means of etching or by means of sawing or bymeans of a suitable laser treatment.

According to an embodiment example, the electronic chips can be used assensors or actuators in micro-electromechanical systems (MEMS), forexample, as pressure sensors or acceleration sensors. In anotherembodiment example, the electronic chips can be used as semiconductorchips for power applications (especially with vertical current flow orwith electrical contacts on two opposing main surfaces), for example,for automotive applications, and can have, for example, at least oneintegrated insulated gate bipolar transistor (IGBT) or at least oneintegrated diode. It is also possible that at least a part of theelectronic chips is formed for performance applications, especially as apower semiconductor chip, for example, as a field-effect transistor(especially as MOSFET). According to an embodiment example, at least oneelectronic chip can be a logical IC (for example, with electricalcontacts on only one of two opposing main surfaces) or an electronicchip for high-frequency power connections. Also, it is possible to useelectronic chips as passive components, for example, resistors, coils orcapacitors. The electronic module can be designed with respect to itselectronic performance such as a DC-DC converter.

A semiconductor substrate can be used as a substrate or wafer to formthe electronic chips, preferably a silicon substrate. Alternatively,silicon oxide or another electrically insulating substrate can be used.It is also possible to use a germanium substrate or an III-Vsemiconductor material. For example, exemplary embodiments can berealized in gallium nitride and silicon carbide technology. In addition,exemplary embodiment examples of standard semiconductor processtechnologies can be used, for example a suitable etching technology(showing on isotropic and anisotropic etching, in particular plasmaetching, dry etching, wet etching), structuring technology (which caninvolve lithographic masks) or the separation technologies (such as, forexample, chemical vapor separation (CVD), plasma enhanced chemical vaporseparation (PECVD), atomic layer separation (ALD), sputtering, etc.).

The above described and other objectives, characteristics and advantageswill become more recognizable on the basis of the following descriptionand the accompanying patent claims, if they will be considered inrelation to the attached drawings, in which appropriate parts orelements with appropriate references are provided.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments are illustrated in the figures and will bediscussed in detail below.

It shows:

FIG. 1: a cross-sectional view of an electronic module according to anexemplary embodiment example.

FIG. 2 to FIG. 11: Cross-section views of structures, which during aprocess for the manufacturing of electronic modules are obtained inaccordance with an exemplary embodiment example.

DETAILED DESCRIPTION OF EMBODIMENT EXAMPLES

The same or similar components in different figures are provided withthe same reference numbers.

FIG. 1 illustrates a cross-sectional view of an electronic module 100according to an exemplary embodiment example.

The electronic module 100 shown in FIG. 1 has a first substrate 102designed as a structured copper foil, a related first dielectric layer104′ made of adhesive resin on the first substrate 102 and twoelectronic chips 106 designed here as a MOSFET power semiconductorchips. Each of the electronic chips 106 is mounted with one or two pads171, 173, 175 on its first main surface 108 directly on a section areaof the first dielectric layer 104′.

The electronic module 100 has also a second substrate 110, designed as astructured copper foil, and a related second dielectric layer 112′ madeof adhesive resin on the second substrate 110. Thus the first substrate102 and the second substrate 110 are designed of an electricallyconductive and thermally conductive material. On the other hand, thefirst dielectric layer 104′ and the second dielectric layer 112′ aredesigned of an electrically insulating material. The materials of thefirst dielectric layer 104′ and the second dielectric layer 112′ can besoft to provide a good adhesive ability during the applying and can behardened or dried to the complete manufacturing of the electronic module100. Each of the electronic chips 106 is mounted with one or two pads171, 173, 175 on its second main surface 114 (which is opposite to thefirst main surface 108) directly on a section area of the seconddielectric layer 112′.

In addition, an electric contact 116 of copper is made for electricalcontacting of electronic chips 106 through the first dielectric layer104′ and the second dielectric layer 112′ as electrically conductivestructure. The electrical contacting 116 fills clearance holes 118,which penetrate the first dielectric layer 104′ and the seconddielectric layer 112′. The electronic chips 106 are so mounted betweenthe first dielectric layer 104′ and the second dielectric layer 112′that metal-filled clearance holes 118 are adjacent of a currentrespective of the main surfaces 108, 114 of the respective electronicchip 106 and thus to its respective pads 171, 173, 175.

As it is illustrated in FIG. 1, a part of the first dielectric layer104′ and a part of the second dielectric layer 112′ of the electronicchips 106 remain uncovered. Such uncovered sections of dielectric layers104 ‘, 112’ of the electronic chips 106 connect a dielectric structure120 which is filling hollow spaces between the first dielectric layer104′ and the second dielectric layer 112′. The dielectric structure 120can be designed, for example, as laminate or melting resin foil. Thedielectric structure 120 can be designed as section of a perforated foiland is structured in such a way that it fills the targeted gaps betweenthe electronic chips 106 on the first dielectric layer 104′.

How it is evident on the basis of a first detail 140 and a second detail150 in FIG. 1, in accordance with the execution example, both the firstdielectric layer 104′ and the second dielectric layer 112, eachconsisting of a first part of layer 122, are mounted directly on therespective substrates 102, 110 and a separate second part of layer 124on the first part of layer 122. The first part of layer 122 can bemanufactured from a material that is different from a material of thesecond part of layer 124. It is also possible alternatively that thefirst part of layer 122 and the second part of layer 124 consist of thesame material, but are applied in two separate procedures. It has beenillustrated that thereby the mounting strength and the properorientation of the electronic chips 106 will be particularly beneficial,without the electrical insulation between the electronic chips 106 andthe respective substrates 102, 110 is at risk.

Two pads 173, 171 of the two electronic chips 106 are electricallycoupled with each other on their first main surfaces 108 by means of theelectrical contacting 116 and by means of a structured section of thefirst substrate 102. On the other hand, the two electronic chips 106 areeach electrically decoupled on their second main surfaces 114.

A via 130 (as a clearance hole, that is filled with electricallyconductive material) provides electrical coupling of the first substrate102 with the second substrate 110 and extends vertically through thedielectric structure 120. Exposed electrical conductive surfaces on thebottom of the electronic module 100, which are mounted through the firstsubstrate 102 and additional separated electrically conductive material,are covered with an electrical connector structure 134, designed here inthe form of solder structures, to connect electrically the electronicmodule 100 with an electronic peripheral device not illustrated in FIG.1 (in particular to solder it thereto). The top and bottom of theelectronic module 100 (with the exception of the electrical connectorstructure 134) can be covered with a protective layer 132 (which can bealso called passivation layer) to protect the electronic module 100mechanically and to isolate it electrically. Optionally also the sideareas of the electronic module 100 can be covered with a such protectionlayer 132, what, according to FIG. 1, due to the lateral continuouslyelectrically insulating layers is not necessary.

Thus, FIG. 1 illustrates the electronic module 100 with the electronicchips 106 designed as semiconductor chips between the first substrate102 as structured lower conductive layer and the second substrate 110 asstructured upper electrically conductive layer. The two electronic chips106 are adjusted in opposite directions to each other. Between the frontand the back side of the electronic chips 106, on the one hand, and thesubstrates 102, 110, on the other hand, the dielectric layers 104′, 112′are included as hardened polymer layers. Each of the dielectric layers104′ and 112′ is designed in accordance with the embodiment example oftwo separate parts of layer 122, 124 with different materialcompositions. Metal vias as part of the electrical contacting 116penetrate the dielectric layers 104, 112 in the form of the clearanceholes 118 to connect electrically the two electronic chips 106 of twomain surfaces 108, 114 with the electrically conductive layers in theform of the substrates 102, 110.

As illustrated in FIG. 1, the relevant dielectric layer 104 ‘, 112’ ofthe electronic module 100 with the exception of electrical contacts (seereference marks 116, 118, 130) is mounted with full surface between theindividual sections of the first substrate 102 on the one hand and theelectronic chips 106/the dielectric structure 120 on the one hand orbetween the individual sections of the second substrate 112 on the onehand and the electronic chips 106/dielectric structure 120 on the otherhand. Thus, the first dielectric layer 104′ extends on the firstsubstrate 102 over a surface area, which exceeds the overall length ofthe first main surface 108. In other words, the first dielectric layer104′ is so extensively mounted, that it is mounting more structuralcomponents of the electronic module 100 on the first substrate 102 overthe mounting of electronic chips 106 on the first substrate 102.Similarly, the second dielectric layer 112′ extends on the secondsubstrate 110 over a surface area, which exceeds the overall length ofthe second main surface 114. In other words, the second dielectric layer112′ is mounted so extensively, that it is mounting more structuralcomponents of the electronic module of the second substrate 110 over themounting of electronic chips 106 on the second substrate 110.

On the electronic module 100, electronic chips 106 are designed as fieldeffect transistors (MOSFET). A particular drain pad is 171 is markedwith reference mark 171, a particular source pad with reference mark 173and a particular gate pad is marked with reference mark 175. Figureillustrates that one of the electronic chips 106 is arranged with itsactive side upwards, the other with its active site is arrangeddownwards.

FIG. 2 to FIG. 11 illustrate cross-sectional views of structures, whichduring the method for the manufacturing of electronic modules 100 areobtained in accordance with an exemplary embodiment example.

In the description of the electronic module 100, referring to FIG. 1, itwas spoken about dielectric layers 104′, 112′. Dielectric layers 104 ‘,112’ can be obtained, when adhesion layers 104, 112 which were mountedduring the manufacturing process and afterwards closer described will behardened.

To get a structure 200 illustrated in FIG. 2, a foil layer stack as afirst substrate 102 is provided. Optionally (for example using drilling,or etching, or a laser treatment, for example an UV-laser treatment), ina main surface of the first substrate 102, a plurality of blind holes202 (as pre-structures, which later can be used as a base for makingopenings, for example, two-dimensional holes or vias, for the rearcontact of electronic chips 106) or at least an alignment mark 204 (herein the form of a register hole). The alignment marks 204 can be used asan alignment aid when placing the electronic chips 106 (see FIG. 4),when mounting a dielectric structure 120 (see FIG. 6), in thecomposition of vias (see FIG. 8) or be used in lithographic etching ofelectrical conductive structures (see FIG. 10), to perform exactlyposition of the corresponding procedure. The blind holes 202 serve asrear connectors for the electronic chips 106.

FIG. 2 illustrates a detail 280, representing a top view of the firstmain surface of the first substrate 102. There also a component mountingarea 260 is illustrated which corresponds to the main part of the firstmain surface of the first substrate 102, except only a ring-shaped edgearea 250 and alignment marker 270 in the central area. The structureillustrated in FIG. 2 200 corresponds to a small central section of thecomponent mounting area 260 of the first substrate 102, that can bedimensioned for example with a length of 40 cm and a width of 20 cm. Thecomponent mounting area 260 corresponds to the range of the firstsubstrate 102, which after the processing and separating, how asreferring to FIG. 11 closer described, a basis for the individualelectronic modules to be manufactured. This component mounting area 260will be, how referring to FIG. 3 described in more detail, completely orfully covered with adhesive material. The same applies to a belowdescribed second substrate 110 (see FIG. 6), which component mountingarea 260 will be also completely or fully covered with adhesivematerial.

Another detail 290 in accordance with FIG. 2 illustrates that the firstsubstrate 102 upon closer inspection as a layer stack can be made ofthree components. A temporary carrier 102 c is a copper structure(alternatively made of aluminum or nickel) with a thickness of forexample 70 μm. One carrier 102 b, for example, only a few nanometersthick, separates the temporary carrier 102 c by a functional layer 102a, which can be, for example, a copper layer with a thickness of 9 μm.The temporary carrier 102 c simplifies the handling of the thin firstsubstrate 102 for the chip mounting. The providing of the separationlayer 102 b allows a detachment of the temporary carrier 102 c from thefunctional layer 102 a (see junction from FIG. 7 to FIG. 8). It ispossible, that the blind holes 202 and the alignment marks 204 extendonly through the functional layer 102 a, but not through the temporarycarrier 102 c.

To get a structure 300 illustrated in FIG. 3 starting from the structure200, a first adhesion layer 104 will be mounted fully on the firstsubstrate 102 by means, for example, of pressing, or separating, orlamination (i.e. connection by pressing under high pressure) to coverits component mounting area 260 completely and fully. In particular alsothe blind holes 202 will be covered with the adhesive material (such asresin) of the first adhesion layer 104. The material of the firstadhesion layer 104 can be optionally pre-dried or treated in any otherway, so that it retains even a desired level of stickiness. For example,a thickness of the first adhesion layer 104 can be adjusted in a rangebetween 5 μm and 100 μm (as well as a thickness of a second adhesionlayer 112, which will be mounted in a later process step), in particularin a range between 20 μm and 30 μm.

It is also optionally possible to mount the first adhesion layer 104from two partial layers (see reference marks 122, 124 in FIG. 1),wherein the first partial layer can be treated at first (for example,can be pre-dried), before the second partial layer is mounted.

To get a structure 400 illustrated in FIG. 4 starting from the structure300, a plurality of electronic chips 106 will be put on the firstadhesion layer 104 with their respective first main surfaces 108 andthereby attached by means of glue and mounted on the first substrate102. The mounting of electronic chips 106 on the sticky and still wetfirst adhesion layer 104 can be done by means of a Pick & Place machinewith a high speed. During this procedure, the alignment of theelectronic chips 106 relative to the first adhesion layer 104 and thefirst substrate 102 can be performed using the alignment marks 204.

To get a structure 500 illustrated in FIG. 5 starting from the structure400, the material of the first adhesion layer 104 will be at leastpartially dried or at least partially hardened to remove containedsolvent in the adhesive material, to improve the handling of the alreadymounted electronic chips 106 and to strengthen the adhesion.

To get a structure 600 illustrated in FIG. 6 starting from the structure500, at first, the second substrate 110 which is mounted as foil stackin its component mounting area 260 (see according to detail 280 in FIG.2) will be fully equipped with a second adhesion layer 112 made fromadhesive material.

A detail 650 according to FIG. 6 illustrates that the second substrate110 upon closer inspection can be designed as a layer stack of threecomponents. A temporary carrier 110 c is a copper structure with athickness of, for example, 70 μm (alternatively made of aluminum ornickel). One carrier layer 110 b, for example, only a few nanometersthick, separates the temporary carrier 110 c by a functional layer 110a, which can be, for example, a copper layer with a thickness of 9 μm.The temporary carrier 110 c simplifies the handling of thin secondsubstrate 110 during the bonding. The providing of the separation layer110 b allows a detachment of the temporary carrier 110 c from thefunctional layer 110 a (see junction from FIG. 7 to FIG. 8).

Although this is not illustrated in the figure, is it optionallypossible to mount one or more electronic chips 106 on the formation ofthe second substrate 110 and the second adhesion layer 112 before theformation of the second substrate 110 and second adhesion layer 112 willbe mounted on the formation of the first substrate 102 and the firstadhesion layer 100 of the electronic chips 106 being mounted together.

The structure 500 according to FIG. 5 is connected with the secondsubstrate 110 covered with a second adhesion layer 112, wherein thehollow spaces between them will be filled through a dielectric structure120. The dielectric structure 120 can be provided in the form ofindividual bodies or as structured or perforated layer and be made, forexample, of prepreg material.

In this connection process, the second main surfaces 114 of theelectronic chips 106 will be simultaneously connected with differentsections of the second adhesion layer 112, as is illustrated in astructure 700 in FIG. 7. Because an additional electrically insulatinglayer in the form of adhesion layers 104, 112 is imprinted on therespective substrates 102, 110, it is beneficial, for example, justexactly one structured layer of prepreg as a dielectric structure 120being sufficient to laminate the two substrates 104, 110 with each otherincluding their mounting. The lamination can be done by means of avacuum PCB laminator press. The layer of prepreg can also be replacedthrough a structured core layer. Although this is not illustrated in thefigure, it is also possible to mount more electronic chips 106 on thesecond substrate 110 before mounting the substrates 102, 110 with eachother.

To get a structure 800 illustrated in FIG. 8 starting from the structure700, at first the temporary carriers 102 c, 110 c will be taken off orremoved. In addition, clearance holes 118 to form micro vias will becreated by means of etching or laser drilling, which extend through thesubstrates 102, 110 and adhesion layers 104, 112. Alternatively, it ispossible to make the clearance holes 118 in the remains of thesubstrates of 102, 110 previously. Also a cleaning process can becarried out, if necessary.

To get a structure 900 illustrated in FIG. 9 starting from the structure800, electrically conductive material on two opposite main surfaces ofthe structure 800 will be separated to make electrical contacts 116 inthe clearance holes 118 and to increase the thickness of the substrates102, 112. At first, a germ layer to the front and to the back can bemade using an electro-less copper separation process, and after that canbe continued with an electrochemical separation process or with a directmetal separation process.

To get a structure 1000 illustrated in FIG. 10 starting from thestructure 900, the thickened substrates 102, 110 in accordance with theprocess of FIG. 9 will be structured, for example, by means oflithography or etching method, wherein the individual pads of eachelectronic chips 106 stay electrically coupled with each other in adesired manner to one part or will be electrically decoupled from eachother to another part. As an alternative to suchdeveloping-etching-stripping method, even a structured separation methodcan be used.

Although this is not illustrated in the figure, it is possible to mountmore layers on the upper or lower side of the structure 1000. It is alsopossible to install solder structures, to perform a finishing process,etc.

To get the electronic modules 100 illustrated in FIG. 11 starting fromthe structure 1000, the structure 1000 will be separated on separatinglines 1002, for example, by means of etching, laser treatment, orsawing, wherewith the electronic modules 100 will be singularized.

A conversion of the adhesion layers 104, 112 (compare FIG. 3 to FIG. 11)in the dielectric layers 104′, 112′ (compare FIG. 1), in particularthrough hardening, can be performed to one or more different timesduring the manufacturing method (for example, in the phase in accordancewith FIG. 5, FIG. 7, FIG. 8 and/or FIG. 11, or in other phases).

Instead of the processes referring to described in FIG. 9 to FIG. 11, itis alternatively possible to use other contact manufacturing methods, asthey are known from the conventional printed circuit technology.

The description referred to in FIG. 2 to FIG. 11 illustrates that alarge part of the processes for the production of electronic modules100, according to exemplary embodiment examples, can be performed asbatch-process, i.e. for many electronic modules 100 in a common parallelmanufacturing method. However, it is also possible to perform individualof the listed above processes only after singularizing, for example, themounting of solder structures (see reference mark 134 in FIG. 1).

A professional will recognize that many alternatives to the describedmanufacturing methods are possible. According to another option, it ispossible, at first, to mount the electronic chips 106 to the adhesionlayers 104, 112 with heat. In addition, it is possible to mountmultiple-layer adhesion layers 104, 112, wherein a first respectivemounted part of layer can be at first hardened, before a respectivedifferent part layer is mounted. In this case, it may be possible toomit a dielectric structure 120 at all. It is also possible topre-laminate a dielectric structure 120 (for example made as a corelayer) before the actual bonding. In addition, it is possible to arrangethe electronic chips 106 on still wet adhesion layers 104, 112 beforethe adhesive material is hardened. It is possible to bond electronicchips 106 on two opposite substrates 102, 110 by the means of theadhesion layers 104, 112. A front side-back side connection can be madeby means of drilled or etched clearance holes.

In addition, it shall be pointed out that “comprising” does not excludeany other elements or steps and “one” or “a” do not exclude anyplurality. It also should be pointed out that features or steps, whichhave been described with reference to one of the above embodimentexamples, can be used also in combination with other features or stepsof other of the embodiment examples described above. Reference marks inthe claims shall not be understood as restrictions.

1. Electronic module, comprising: a first substrate; a first dielectriclayer on the first substrate; at least an electronic chip, which ismounted with a first main surface directly or indirectly on a section ofthe first dielectric layer; a second substrate over a second mainsurface of the at least one electronic chip; an electrical contactingfor electrically contacting the at least one electronic chip through thefirst dielectric layer; wherein the first dielectric layer on the firstsubstrate extends across an area, which exceeds the first main surface.2. Electronic module according to claim 1, comprising a seconddielectric layer on the second substrate, wherein the at least oneelectronic chip is mounted with its second main surface directly orindirectly on a section of the second dielectric layer.
 3. Electronicmodule according to claim 1, wherein at least one of the first substrateand of the second substrate is a structured foil.
 4. Electronic moduleaccording to claim 1, wherein the first dielectric layer is formed of afull-surface layer with at least one through-hole, which is filled withan electrically conductive material, as electrical contact forelectrically contacting the first main surface of the at least oneelectronic chip.
 5. Electronic module according to claim 1, comprising aplurality of electronic chips, wherein each of them is mounted with itsfirst main surface on the first dielectric layer in such way, that apart of the first dielectric layer remains uncovered of the plurality ofelectronic chips.
 6. Electronic module according to claim 1, wherein theat least one electronic chip is configured as a power semiconductorchip.
 7. Electronic module according to claim 2, comprising a dielectricstructure, in particular a laminate structure, to fill in particularcompletely at least one hollow space, which is delimited between thefirst dielectric layer, the second dielectric layer and the at least oneelectronic chip.
 8. Electronic module according to claim 1, wherein thefirst dielectric layer is formed by a first partial layer on the firstsubstrate and a separate second partial layer on the first partiallayer.
 9. Electronic module according to claim 1, comprising twoelectronic chips, wherein one of them has its active side on its firstmain surface and the other one has its active side on its second mainsurface.
 10. Electronic module according to claim, comprising aplurality of electronic chips, which are electrically coupled with eachother on at least one of the first main surface and the second mainsurface by the electrical contacting.
 11. Electronic module according toclaim 1, comprising at least one through hole filled with electricallyconductive material, which extends perpendicular to the first substrateand the second substrate to form an electrical coupling of the firstsubstrate with the second substrate.
 12. Method of manufacturing atleast one electronic module, wherein the method comprises: applying afirst adhesion layer at least to an entire component mounting area of afirst substrate; direct or indirect mounting of a first main surface ofat least one electronic chip on a partial region of the first adhesionlayer; arranging a second substrate over a second main surface of the atleast one electronic chip; electrical contacting of the at least oneelectronic chip through the first adhesion layer.
 13. Method accordingto claim 12, further comprising: applying a second adhesion layer on asecond substrate; direct or indirect mounting of the second main surfaceof at least one electronic chip on a section of the second adhesionlayer.
 14. Method according to claim 13, wherein the second adhesionlayer is applied at least to an entire component mounting area of thesecond substrate.
 15. Method according to claim 13, wherein at least oneof the first adhesion layer and of the second adhesion layer is appliedessentially completely on the respective substrate.
 16. Method accordingto claims 13, wherein at least one through hole for electricallycontacting the respective main surface of the respective electronic chip(106) is formed in at least one of the first adhesion layer (104) and ofthe second adhesion layer (112).
 17. Method according to claim 16,wherein the at least one through hole for electrically contacting therespective main surface of the respective electronic chip is filled atleast partially with electrically conductive material.
 18. Methodaccording to claim 13, wherein at least one of the first adhesion layerand of the second adhesion layer is mounted in a two-phase process onthe respective substrate (102, 110), wherein at first in a first phase,a first partial layer is mounted on the respective substrate, and thenin a separate and subsequent second phase, a second partial layer ismounted on the first partial layer.
 19. Method according to claim 12,wherein at least one of the first substrate and of the second substrateis structured, in particular by etching, to thus form electricallyconductive paths.
 20. Method according to claim 12, comprising asingularizing of a plurality of electronic chips between the firstsubstrate and the first adhesion layer, on the one hand, and the secondsubstrate, on the other hand, to a plurality of electronic modules,wherein each of them comprises at least a section of the firstsubstrate, a section of the first adhesion layer, a section of thesecond substrate and at least one electronic chip.
 21. Method formanufacturing at least one electronic module, wherein the methodcomprises: applying a first adhesion layer at least to an entirecomponent mounting area of a first substrate; direct or indirectmounting a first main surface of a plurality of electronic chips on arespective partial region of the first adhesion layer; arranging asecond adhesion layer on a second substrate; direct or indirect mountinga second main surface of a plurality of electronic chips on a respectivepartial region of the second adhesion layer.
 22. Method according toclaim 21, wherein the second adhesion layer is applied at least to anentire component mounting area of the second substrate.
 23. Methodaccording to claim 21, wherein at least one of the first adhesion layerand of the second adhesion layer is applied essentially completely onthe respective substrate.
 24. Method according to claim 21, wherein atleast one through hole for electrically contacting the respective mainsurface of the respective electronic chip (106) is formed in at leastone of the first adhesion layer (104) and of the second adhesion layer(112).
 25. Method according to claim 24, wherein the at least onethrough hole for electrically contacting the respective main surface ofthe respective electronic chip is filled at least partially withelectrically conductive material.
 26. Method according to claim 21,wherein at least one of the first adhesion layer and of the secondadhesion layer is mounted in a two-phase process on the respectivesubstrate (102, 110), wherein at first in a first phase, a first partiallayer is mounted on the respective substrate, and then in a separate andsubsequent second phase, a second partial layer is mounted on the firstpartial layer.
 27. Method according to claim 21, wherein at least one ofthe first substrate and of the second substrate is structured, inparticular by etching, to thus form electrically conductive paths. 28.Method according to claim 21, comprising a singularizing of a pluralityof electronic chips between the first substrate and the first adhesionlayer, on the one hand, and the second substrate, on the other hand, toa plurality of electronic modules, wherein each of them comprises atleast a section of the first substrate, a section of the first adhesionlayer, a section of the second substrate and at least one electronicchip.